ALL
93
Makoto Nagata, "The Graduate School of Science, Technology and Innovation (STIN) at Kobe University," University of Zagreb, 2024.12.9. (Zagreb)92
Makoto Nagata, "Hardware Security and Safety of IC Chips and Systems," IEEE Solid-State Circuits Society, Croatian Chapter DL Seminar, 2024.12.9. (Zagreb)91
Makoto Nagata, "RF Noise Coupling -- Understanding, Mitigation and Impacts on Wireless Communication Performance of IC Chips and Systems (Short version)," Tyndall National Institutes/University College Cork, IEEE SSCS DL Talk, 2024.10.30. (Cork)90
Makoto Nagata, "Hardware Security and Safety of IC Chips and Systems," IEEE Solid-State Circuits Society, UK/Ireland Chapter DL Seminar, 2024.10.29. (Cork)89
Makoto Nagata, "Hardware Security and Safety of IC Chips and Systems," IEEE Solid-State Circuits Society, Benelux Chapter DL Seminar, 2024.10.28. (Eindhoven)88
Makoto Nagata, "Secure Packaging, Tamper Resistance, and Supply Chain Security of IC Chips," IEEE Solid-State Circuits Society, Oregon Chapter DL Seminar, 2024.10.21. (Hillsboro)87
Makoto Nagata, "Chip-Backside Vulnerability to Intentional Electromagnetic Interference in Integrated Circuits (Invited)," the 14th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo 2024), Invited Talk #I, 2024.10.7. (Torino)86
Makoto Nagata, "Si-Substrate Backside of an IC Chip for Performance Improvements and Security (Invited)," IEEE International 3D Systems Integration Conference (3DIC 2024), Invited Talk I, 2024.9.25. (Sendai)85
Makoto Nagata, "Deployment of EMC-Compliant IC Chip Techniques in Design for Hardware Security (Invited)," The 14th International Workshop on EMC (CEM 2024), 2024.9.19. (Sibu, Romania/Hybrid)84
Makoto Nagata, "Hardware Security and Safety of IC Chips and Systems," IEEE Solid-State Circuits Society, Orange County Chapter DL Seminar, 2024.6.4. (Irvine)83
Makoto Nagata, "Hardware Security and Safety of IC Chips and Systems," IEEE Solid-State Circuits Society, San Diego Chapter DL Seminar, 2024.6.3. (San Diego)82
Makoto Nagata, "RF Noise Coupling -- Understanding, Mitigation and Impacts on Wireless Communication Performance of IC Chips and Systems --Short Version," IEEE Solid-State Circuits Society, Grenoble IEEE Student Branch DL Seminar, 2024.4.12. (Grenoble)81
Makoto Nagata, "IC Chip and Packaging Interactions for Performance Improvements and Security Protections," IEEE Solid-State Circuits Society, Grenoble IEEE Student Branch DL Seminar, 2024.4.12. (Grenoble)80
永田真, "半導体チップの先端パッケージング技術とハードウエアセキュリティ," 熊本大学半導体セミナー, 2024.2.7.（オンライン）79
Makoto Nagata, "Si-Substrate Backside of an IC Chip for Performance Improvements and Security," Seminar, KU Leuven, Jan. 2024. (Leuven)Video77
Makoto Nagata, "On-Chip Physical Attack Protection Circuits and Design for Hardware Security," POSTECH, 2023.10.10. (Pohang)76
Makoto Nagata, "On-Chip and In-System Side-Channel Measurements and Assessments," ACM/IEEE Design Automation Conference (DAC 2023), Tutorial, 2023.7.10. (San Francisco) 75
Makoto Nagata, "Hardware Security and Safety of IC Chips (Invited)," The 38th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2023), 2023.6.27. (Jeju)Link74
Makoto Nagata, "Vertically Integrated Si Techniques for Hardware Security Attack Countermeasures (Invited)," International Hardware Security Forum, 2023.6.18. (Kyoto)Link73
Makoto Nagata, "Magnetic Thin Films for In-Package Noise Suppression of Semiconductor Switching Circuits (Invited)," IEEE The 1st International Symposium on Integrated Magnetics (iSIM), B4, 2023.5.14. (Sendai)72
Makoto Nagata, "On-Chip and In-System Side-Channel Measurements and Assessments," IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Tutorial, T7-2, 2023.5.1. (San Jose)71
Takuji Miki, "Cryogenic Bias Voltage Control Circuits for Large Scale Qubit Arrays," 28th Asia and South Pacific Design Automation Conference (ASP-DAC 2023), Jan. 18, 2023.Link70
Makoto Nagata, "Simulating Power Side Channel Leakages from Architectural Exploration to Physical Implementation of Crypto ICs," Ansys IDEAS 2022, Dec. 6, 2022.Link69
Makoto Nagata, "Circuits and Packaging Systems for Security Chips (Invited)," IEEE Asian Solid-State Circuits Conference (A-SSCC), Convergence Workshop, CW-2, 2022.10.9. (Taipei)68
Koh Watanabe, Ryota Sakai, Satoshi Tanaka, Makoto Nagata, "ELECTROMAGNETIC INTERFERENCE OF EMISSION NOISE ON MOBILE COMMUNICATIONS INSIDE INDUSTRIAL UNMANNED AERIAL VEHICLES," The 13th edition of International Workshop of Electromagnetic Compatibility (CEM 2022), Sep. 2022. (Suceava)67
Kazuki Monta, "RTL DESIGN SECURITY VERIFICATION FOR RESISTING POWER SIDE-CHANNEL ATTACK," Ansys Customer Workshop at DAC 2022, Jul. 2022. (San Francisco)66
Kazuki Monta, "Testing Embedded Toggle Pattern Generation Through On-Chip IR Drop Monitoring," Lectures In the frame of Erasmus+ International program, 2022.06.30. (Thessaloniki)Link65
Makoto Nagata, "Hardware Security and Safety of IC Chips," Lectures In the frame of Erasmus+ International program, 2022.06.30. (Thessaloniki)Link64
Makoto Nagata, "On-Chip and In-System Side-Channel Measurements and Assessments," ACM/IEEE 27th Asia and South Pacific Design Automation Conference (ASP-DAC 2022), Tutorial talk, 2022.1.17. (Online)63
Makoto Nagata, "Deployment of EMC-Compliant IC Chip Techniques in Design for Hardware Security," IEEE Solid-State Circuits Society, Japan Chapter Virtual DL Seminar, 2021.12.24.62
Makoto Nagata, "RF Noise Coupling -- Understanding, Mitigation and Impacts on Wireless Communication Performance," IEEE Solid-State Circuits Society, Taipei Chapter Virtual DL Seminar, 2021.12.7.61
Makoto Nagata, "Chip Stacking and Packaging Technology Explorations for Hardware Security (Invited Talk)," The 23rd ACM/IEEE International Workshop on System-Level Interconnect Pathfinding (SLIP 2021), 2021.11.4. (Virtual event)60
Hiroki Sonoda, Kazuki Monta, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Noriyuki Miura, Takuji Miki and Makoto Nagata, "Secure 3D CMOS Chip Stacks with Backside Buried Metal Power Delivery Networks for Distributed Decoupling Capacitance [IEDM]", IEEE EDS Kansai Chapter, IEEE EDS 第21 回関西コロキアム電子デバイスワークショップ, 202109.28. (オンライン)59
Makoto Nagata, "Side-channel Leakages, Attacks and Simulation for Hardware Security," IEEE 47th European Solid-State Circuits Conference (ESSCIRC 2021), Educational Event #12.10, Sep. 2021. (Virtual conference)58
Makoto Nagata, "On-Chip Physical Attack Protection Circuits for Hardware Security," IEEE Solid-State Circuits Society, Singapore Chapter Virtual DL Seminar, 2021.9.657
Makoto Nagata, "IC-Chip Level Physical Attack Protections for IoT Security," NXP, 2XP Distinguished Lecturer Series Virtual Seminar, 2021.7.13.56
Makoto Nagata, "RF Noise Coupling - Understanding, Mitigation and Impacts on Wireless Communication Performance," IEEE Solid-State Circuits Society, Poland Chapter Virtual DL Seminar, 2021.6.24.55
Makoto Nagata, "IC Chip and Packaging Interactions in Design for SI, PI, EMC and ESD," IEEE Solid-State Circuits Society, Poland Chapter Virtual DL Seminar, 2021.6.15.54
Makoto Nagata, "IC-Chip Level Physical Attack Protections for IoT Security," 2021 Symposia on VLSI Technology and Circuits, Short course, SC3-6, 2021.6. 14. (Virtual conference)53
Makoto Nagata, "Hardware Security and Safety of IC Chips" IEEE Solid-State Circuits Society, Israel Chapter Virtual DL Seminar, 2021.6.8.Link to event52
Makoto Nagata, "RF Noise Coupling - Understanding, Mitigation and Impacts on Wireless Communication Performance," IEEE Solid-State Circuits Society, Beijing Chapter Virtual DL Seminar, 2021.5.25.51
Makoto Nagata, "IC Chip and Packaging Interactions in Design for SI, PI, EMC and ESD," IEEE Solid-State Circuits Society, Switzerland Chapter Virtual DL Seminar, 2021.4.22.50
Makoto Nagata, "Hardware Security and Safety of IC Chips," IEEE Solid-State Circuits Society, Webinar, 2021.4.16.Link to eventLink to video49
Makoto Nagata, "IC Chip and Packaging Interactions in Design for SI, PI, EMC and ESD," IEEE Solid-State Circuits Society, Croatia Chapter Virtual DL Seminar, 2021.2.25.48
Makoto Nagata, "RF Noise Coupling - Understanding, Mitigation and Impacts on Wireless Communication Performance," IEEE Solid-State Circuits Society, Austria Chapter Virtual DL Seminar, 2021.1.15.47
Makoto Nagata, "Deployment of EMC-Compliant IC Chip Techniques in Design for Hardware Security," IEEE Solid-State Circuits Society, Austria Chapter Virtual DL Seminar, 2020.12.4.46
Makoto Nagata, "On-Chip Physical Attack Protection Circuits for Hardware Security," IEEE Solid-State Circuits Society, Seoul Chapter Virtual DL Seminar, 2020.9.1.45
Makoto Nagata, "On-Chip Physical Attack Protection Circuits for Hardware Security," IEEE Solid-State Circuits Society, Bangladesh Chapter Virtual DL Seminar, 2020.7.30.44
Makoto Nagata, "IC Chip and Packaging Interactions in Design for SI, PI, EMC and ESD," IEEE Solid-State Circuits Society, Oregon Chapter Virtual DL Seminar, 2020.6.20.43
Makoto Nagata, "A C-P-S Simulation Technique of Power-Noise Side Channel Leakage in Cryptographic Integrated Circuits," Ansys Simulation World, 2020.6.10,11.On demand here42
Makoto Nagata, "Deployment of EMC-Compliant IC Chip Techniques in Design for Hardware Security," BWRC seminar, University of California at Berkeley, 2020.1.31.41
Makoto Nagata, "Side-Channel Attack Analysis and Simulation Techniques," 33rd International Conference on VLSI Design/19th International Conference on Embedded Design (VLSIdesign 2020), Tutorial, Jan. 2020. (Bangalore)40
Makoto Nagata, "Side Channel Attacks (Invited)," 26th IEEE Electronic Design Process Symposium (EDPS 2019), Oct. 2019. (Milpitas).about event39
Makoto Nagata, "(Invited) Deployment of EMC-Compliant IC Chip Techniques in Design for Hardware Security," The 14th Asia Joint Conference on Information Security (AsiaJCIS 2019), Aug. 2019. (Kobe)about event38
Makoto Nagata, "Power Noise Simulation of IC Chips for Hardware Security," 2019 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+SIPI 2019), Tutorial, FR-AM-3-2, Jul.2019. (New Orleans)37
Makoto Nagata, "Diversity in IC labs.," IEEE Diversity Luncheon at VLSI Symposium, Jun. 2019. (Kyoto)36
Makoto Nagata, "C-P-S Simulation Techniques for Safety and Security," Ansys Workshop at DAC 2019, Jun. 2019. (Las Vegas)35
Makoto Nagata, "Undesired Radio Waves of IoT Devices: Evaluation and Countermeasures (Invited)," The 2nd Croatia - Japan Electromagnetic Compatibility Workshop (CJEMC 2019), May. 2019. (Sendai)34
Makoto Nagata, "Deployment of EMC-Compliant IC Chip Techniques in Design for Hardware Security," The 5th France-Japan Cybersecurity Workshop, May. 2019.workshopaccess to lecture slides33
Makoto Nagata, "Leveraging Chip Power Models for System-Level EMC Simulation of Automotive ICs," ANSYS Webinar, Apr. 2019.about eventaccess to recorded version32
Makoto Nagata, "Deployment of EMC-Compliant IC Chip Techniques in Design for Hardware Security," ECE Seminar, National University of Singapore, Sep. 2018. (Singapore)31
Makoto Nagata, "Simulation Techniques toward Design for Electromagnetic Susceptibility (EMS) of IC Chips," Ansys Workshop at DAC 2018, Jun. 2018. (San Francisco)30
Makoto Nagata, "Toward EMC Compliant Design of IC Chips in Automotive Applications," The 1st Croatia-Japan EMC Workshop, May. 2018. (Zagreb)29
Makoto Nagata, "Challenges: Deployment of EMC-Compliant IC Chip Techniques in Design for Hardware Security," COSIC Seminar, KU Leuven, Mar. 2018. (Leuven)28
Makoto Nagata, "3D Design for Diagnosis and Characterization with In-Place Waveform Capturing (Invited)," MIITEC Advanced Testing Technology Seminar, Dec. 2017. (Nanjing)27
Makoto Nagata, "Protecting Cryptographic Integrated Circuits with Side-Channel Information," 2017 IEEE 12th International Conference on ASIC (ASICON 2017), Tutorial, T-3, Oct. 2017. (Guiyang)26
Akihiro Tsukioka, Kohki Taniguchi, Daisuke Fujimoto, Makoto Nagata, Takao Egami, Reiko Akimoto, Kenji Niinomi, Takeshi Yuhara, Rob Mathews, Karthik Srinivasan, Ying-Shiun Li, Norman Chang, "Simulation Techniques for EMC compliant Design of Automotive IC Chips and Modules," ACM/IEEE Design Automation Conference (DAC 2017), #WIP-120.21 (poster), Jun. 2017. (Austin)25
Makoto Nagata, "Simulation Techniques toward Design for Electromagnetic Susceptibility (EMS) of IC Chips," Ansys Workshop at DAC 2017, Jun. 2017. (Austin)24
Noriyuki Miura, Shijia Liu, Tsuyoshi Watanabe, Shigeki Imai, Makoto Nagata, "A Permanent Digital Archive System Based on 4F^2 X-Point Multi-Layer Metal Nano-Dot Structure," IEEE SSCS Kansai Chapter Technical Seminar, Feb. 2017. (神戸大学・梅田インテリジェントラボラトリ)23
Noriyuki Miura, "Proactive and Reactive Countermeasures against Active and Passive EM Attacks," IEEE International Symposium on Electromagnetic Compatibility (EMC2016), Jul. 2017. (Ottawa, Canada)22
Masahiro Yamaguchi, Satoshi Tanaka, Jingyan Ma, Yasunori Miyazawa, Makoto Nagata,Koichi Kondo, Yasuyuki Okiyoneda, Masahiro Nishizawa, "SiP Packaging-Compatible Magnetic Thin-Film Noise Suppressor to Countermeasure Digital Noise from Power Electronics Devices (invited)," The 7th Asia-Pacific International Symposium on Electromagnetic Compatibility & Signal Integrity and Technical Exhibition (APEMC 2016), TH-AM-Ⅱ-TS02-1, May. 2016. (Shenzhen, China)21
Makoto Nagata, "Noise Simulation in Mixed-Signal SoCs (Invited Tutorial)," 2016 IEEE International Solid-State Circuits Conference (ISSCC 2016), Tutorial, T8, Jan. 2016. (San Francisco)20
Makoto Nagata, "IC Chips to be Dependable, Secure, and Robust (Plenary)," International Technical Conference on Circuits/Systems, Computers and Communcations 2015 (ITC-CSCC 2015), Jul. 2015. (Seoul)19
Makoto Nagata, "Diagnosis, Protection, and Configurability of I/O Circuits for 3D Chip Stacking (Invited)," Design for three dimensional integration (D43D 2015), Jun. 2015. (Grenoble)18
Makoto Nagata, "Securing Cryptographic Engines ? Circuit Techniques against EM Attacks (Invited)," International Symposium on IoT Enabling Chips, Jun. 2015. (Kyoto)17
Makoto Nagata, "IC Chips to Be Dependable, Secure, and Robust," VirginiaTech, CESCA Day 2015, May. 2015. (Bracksburg)16
Nao Ueda, Cesar Roda Neve, Mikael Detalle, Geert Van der Plas, Eric Beyne, Makoto Nagata, "Broadband Metal-Insulator-Metal Capacitors on Silicon Interposer for Low Impedance Power Distribution Network," DATE 2015 Workshop on 3D Integration (3D-WS 2015), #3.4, Mar. 2015. (Grenoble)15
Makoto Nagata, "In-Place Diagnosis of Undesired Power Domain Problems in IC Chips and Stacks," ST Microelectronics, Mar. 2015. (Crolles)14
Makoto Nagata, "IC Chip Immunity Measurements and Analysis," Ansys, Feb. 2015. (San Jose).13
Makoto Nagata, "Side Channel Leakage in Cryptographic Modules: Introduction to Physical Origins and Attack Models (Tutorial)," 20th Asia and South Pacific Design Automation Conference (ASP-DAC 2015), #T4.4, Jan. 2015. (Makuhari)12
Masahiro Yamaguchi, Satoshi Tanaka, Yasushi Endo, Makoto Nagata, Hiroaki Matsui, Mizuki Iwanami, Kenta Tsukamoto, "IC Chip Level Low Noise Technology for High Speed and High Quality Telecommunication Systems," 2014 Asia-Pacific Microwave Conference (APMC), #TH2E-1, Nov. 2014. (Sendai)11
Makoto Nagata, Satoshi Takaya, Hiroaki Ikeda, Dimitri Linten, Mirko Scholz, Shih-Hung Chen, Keiichi Hasegawa, Taizo Shintani, Masanori Sawada, "CDM ESD Testing of a 3D TSV Stacked IC Chip," Fifth IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST), #7-1, Oct. 2014. (Seattle)10
Makoto Nagata, Shunsuke Shimazaki, Naoya Azuma, Noriyuki Miura, Sho Muroga, Yasushi Endo, Satoshi Tanaka, Masahiro Yamaguchi, "Measurements and Simulation of RF Noise Coupling and Its Impacts on LTE Wireless Communication Performance (Invited)," 2014 International Symposium on Electromagnetic Compatibility, Tokyo, #14P1-B2W, May. 2014. (Tokyo)9
Makoto Nagata, "Power Noise Awareness in Design and Diagnosis of VLSI Systems," 2014 18th IEEE Workshop on Signal and Power Integrity (SPI 2014), #SS-2, May. 2014. (Ghent)8
Makoto Nagata, "Power Noise Awareness in Design and Diagnosis of VLSI Systems," 2013 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), Keynote Speech III, Dec. 2013. (Nara)7
Makoto Nagata, Sathoshi Takaya, Hiroaki Ikeda, "In-Place Signal and Power Noise Waveform Capturing within 3D Chip Stacking," Fourth IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST), #5-2, oral presentation, Sep. 2013. (Anaheim)6
Makoto Nagata, Sathoshi Takaya, Hiroaki Ikeda, "In-Place Signal and Power Noise Waveform Capturing within 3D Chip Stacking," 2013 IEEE International Test Conference (ITC 2013), PO-27, poster presentation, Sep. 2013. (Anaheim)5
Makoto Nagata, "Power-Noise Measurements and Simulation Techniques for Side-Channel Analysis," 2013 IEEE International Symposium on Electromagnetic Compatibility (EMC 2013), Tutorials MO-AM-4-3, tutorial talk 45 min, Aug. 2013. (Denver)4
Makoto Nagata, Sathoshi Takaya, Atsushi Sakai, Shiro Uchiyama, Harufumi Kobayashi, Hiroaki Ikeda, "Design Strategies using 2D Toolsets for 3D TSV Chip Stacks featuring 4096b Wide I/O at 100GB/s," Design Automation Conference 2013 (DAC 2013), Designer Track #7.29, poster presentation, Jun. 2013. (Austin)3
Daisuke Fujimoto, Daichi Tanaka, Makoto Nagata, "A Simulation Methodology Aearching Side-Channel Leakage Using Capacitor Charging Model," The 7th International Workshop on Security (IWSEC2012), poster presentation, Nov. 2012. (Fukuoka)2
Satoshi Takaya, Takashi Hasegawa, Yoji Bando, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Souda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata, "Variation of Substrate Sensitivity in Differential Pair Transistors," IEEE Workshop on Variability Modeling and Characterization (VMC, colocated workshop of ICCAD2011), Nov. 2011. (San Jose)1
Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Akihiro Sasaki, Yohei Hori, Akashi Satoh, "A Fast Power Current Analysis Methodology using Capacitor Charging Model for Side Channel Attack Evaluation," CHES2011, Poster presentation, Sep. 2011. (奈良東大寺)