Graduate School of Science, Technology and Innovation, Kobe University
Télécom Paris’ (Prof. Jean-Luc Danger), FranceSPACES Project (URL)
Makoto Nagata, Jean-Luc Danger, Noriyuki Miura, “Creating a Safe and Robust Digitally-Connected World,” Impact, Vol. 2018, No. 11, pp. 22-25, Dec. 2018, Science Impact Ltd. DOI:10.21820/23987073.2018.11.22 (URL)
IMEC (Dr. Erik Jan Marinissen, Dr. Geert Van der Plas), BelgiumYuuki Araga, Makoto Nagata, Joeri De Vos, Geert Van der Plas, Eric Beyne, “A Study on Substrate Noise Coupling among TSVs in 3D Chip Stack,” IEICE Electronics Express, Vol. 15, No. 13, pp. 1-8, Jul. 2018. DOI:10.1587/elex.15.20180460
Yuuki Araga, Makoto Nagata, Geert Van der Plas, Paul Marchal, Michael Libois, Antonio La Manna, Wenqi Zhang, Gerald Beyer, Eric Beyne, “Measurements and Analysis of Substrate Noise Coupling in TSV based 3D Integrated Circuits,” IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 4, No. 6, pp. 1026-1037, June 2014. DOI: 10.1109/TCPMT.2014.2316150
ANSYS (Dr. Norman Chang), Semiconductor Business Unit, USAkihiro Tsukioka, Karthik Srinivasan, Shan Wan, Lang Lin, Ying-Shiun Li, Norman Chang, Makoto Nagata, “A Fast Side-channel Leakage Simulation Technique Based on IC Chip Power Modeling,” IEEE Letters on Electromagnetic Compatibility Practice and Applications (L-EMCPA), vol. 1, no. 4, pp. 83-87, Dec. 2019. DOI: 10.1109/LEMCPA.2020.2978624
Makoto Nagata, “Leveraging Chip Power Models for System-Level EMC Simulation of Automotive ICs,” ANSYS Webinar, Apr. 2019. (about event , access to recorded version )
CPSEC (Cyber Physical Security Research Center), AIST, Japan