Journal papers | Nagata and Miki Laboratory, Kobe Univ.

001

田口美里、高橋亮蔵、加藤薫子、楠野順弘、三木拓司、永田真, "量子コンピュータ向けフリップチップシリコンインターポーザの極低温評価," 電子情報通信学会論文誌C, Vol. J107-C, No. 4, pp. pp.175-181, Apr. 2024.DOI: 10.14923/transelej.2023JCP5008

002

永田真、” 無線通信を利用する自律移動体の電磁ノイズ課題と解決に向けて（招待論文）,” 電子情報通信学会論文誌B, vol. J-106B, no. 8, pp. 440-408, Aug. 2023.DOI: 10.14923/transcomj.2022PEI0003

003

Makoto Nagata, "Design of Circuits and Packaging Systems for Security Chips (Invited)," IEICE Transactions on Electronics, Vol. E106.C, No. 7, pp. 345-351, July 2023.DOI: 10.1587/transele.2022CDI0001

004

Takuya Wadatsumi, Kohei Kawai, Rikuu Hasegawa, Kikuo Muramatsu, Hiromu Hasegawa, Takuya Sawada, Takahito Fukushima, Hisashi Kondo, Takuji Miki, Makoto Nagata, "Experimental Exploration of the Backside ESD Impacts on an IC Chip in Flip Chip Packaging," IEICE Transactions on Electronics(Early access), Apr. 2023.DOI: 10.1587/transele.2022CTP0004

005

Ryozo Takahashi, Takuji Miki, Makoto Nagata, "An Analog Side-channel Attack on a High-speed Asynchronous SAR ADC using Dual Neural Network Technique," IEICE Transactions on Electronics(Early access), Apr. 2023.DOI: 10.1587/transele.2022CTS0002

006

Kazuki Monta, Lang Lin, Jimin Wen, Harsh Shrivastav, Calvin Chow, Hua Chen, Joao Geada, Sreeja Chowdhury, Nitin Pundir, Norman Chang, Makoto Nagata, "Silicon-correlated Simulation Methodology of EM Side-channel Leakage Analysis," ACM Journal on Emerging Technology in Computing System, vol. 19, no. 1, Article 9, Jan. 2023, 23 pages.DOI: 10.1145/3568957

007

Makoto Nagata, Noriyuki Miura, Takuji Miki, "Analog Techniques for Digital Security," IEEE Solid-State Circuits Magazine, vol. 15, no. 1, pp. 25-31, Jan. 2023.DOI: 10.1109/MSSC.2022.3219780

008

渡邊航、酒井陵多、青井舞、小松美早紀、田中聡、永田真, "産業用ドローンの近傍における放射電磁ノイズの広帯域評価と移動通信干渉の解析," 電子情報通信学会論文誌B, Vol. J106-B, No. 3, pp. 178-186, Mar. 2023.DOI: 10.14923/transcomj.2022GWP0009

009

Kazuki Monta, Leonidas Kataselas, Ferenc Fodor, Takuji Miki, Alkis Hatzopoulos, Makoto Nagata, Erik Jan Marinissen, "Testing Embedded Toggle Generation Through On-Chip IR Drop Measurements," in IEEE Design & Test, vol. 39, no. 5, pp. 79-87, Oct. 2022.DOI: 10.1109/MDAT.2022.3178050

010

Koh Watanabe, Misaki Komatsu, Mai Aoi, Ryota Sakai, Satoshi Tanaka, Makoto Nagata, "Analysis of Electromagnetic Noise from Switching Power Modules using Wide Band Gap Semiconductors," in IEEE Letters on Electromagnetic Compatibility Practice and Applications (LEMCPA), vol. 4, no. 4, pp.92-96, Dec. 2022.DOI: 10.1109/LEMCPA.2022.3207234

011

Hiroki Sonoda, Ryo Kasai, Daisuke Tanaka, Yoshihide Murakami, Kyoshi Mihara, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Takuji Miki, Makoto Nagata, "In-Place Evaluation of Powering and Signaling Within Fan-Out Multiple IC Chip Packaging," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 12, no. 7, pp. 1140-1149, Jul. 2022.DOI: 10.1109/TCPMT.2022.3179149

012

Takuji Miki, Ryozo Takahashi, Makoto Nagata, "An 11-bit 0.008mm2 charge-redistribution digital-to-analog converter operating at cryogenic temperature for large-scale qubit arrays," IEICE Electronics Express, vol.19, no.8, Apr. 2022.DOI: 10.1587/elex.19.20220099

013

Takuji Miki, Makoto Nagata, "Countermeasures against physical security attacks on ICs utilizing on-chip wideband ADCs," Japanese Journal of Applied Physics, vol. 61, no. SC0803, pp. 1-8, 2022.DOI: 10.35848/1347-4065/ac4823

014

Hiroki Sonoda, Takuji Miki, Makoto Nagata, "Measurement of Electromagnetic Field Immunity of Voltage-Controlled Oscillator-Based Analog-to-Digital Converters in 28 nm CMOS Technology," Japanese Journal of Applied Physics, Vol. 61, No. SC1045, pp. 1-7, Feb. 2022.DOI: 10.35848/1347-4065/ac48d5

015

Makoto Nagata, Takuji Miki, Noriyuki Miura, "Physical Attack Protection Techniques for IC Chip Level Hardware Security" IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, no. 1, pp. 5-14, Jan. 2022.DOI: 10.1109/TVLSI.2021.3073946

016

Yuuki Araga, Ryo Kasai, Daisuke Tanaka, Yoshihide Murakami, Kyoshi Mihara, Kazuo Makida, Hiroki Sonoda, Makoto Nagata, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, "Landside Capacitor Efficacy Among Multi-Chip-Module Using Si-Interposer," IEICE Electronics Express, vol.18, no.9, May 2021.DOI: 10.1587/elex.18.20210070

017

Tsutomu Matsumoto, Makoto Ikeda, Makoto Nagata, Yasuyoshi Uemura, "Secure Cryptographic Unit as Root-of-Trust for IoT Era," IEICE Transactions on Electronics, vol. E104-C, no. 7, pp. 262-271, Jul. 2021.DOI: 10.1587/transele.2020CDI0001

018

Kazuki Monta, Hiroki Sonoda, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Noriyuki Miura, Takuji Miki, Makoto Nagata, "3-D CMOS Chip Stacking for Security ICs Featuring Backside Buried Metal Power Delivery Networks With Distributed Capacitance," IEEE Transactions on Electron Devices, vol. 68, no. 4, pp. 2077-2082, Apr. 2021.DOI: 10.1109/TED.2021.3058226

019

Takuya Wadatsumi, Takuji Miki, Makoto Nagata, "A dual-mode successive approximation register analog to digital converter to detect malicious off-chip power noise measurement attacks," Japanese Journal of Applied Physics (JJAP), vol. 60, no. SB, pp. SBBL03_1-9, Feb. 2021.DOI: 10.35848/1347-4065/abde26

020

Sho Tada, Yuki Yamashita, Kohei Matsuda, Makoto Nagata, Kazuo Sakiyama, Noriyuki Miura, "Design and Concept Proof of an Inductive Impulse Self-Destructor in Sense-and-React Countermeasure Against Physical Attacks," Japanese Journal of Applied Physics (JJAP), vol. 60, no. SB, pp. SBBL01_1-8, Feb. 2021.DOI: 10.35848/1347-4065/abdf1f

021

Shoei Nashimoto, Daisuke Suzuki, Noriyuki Miura, Tatsuya Machida, Kohei Matsuda, Makoto Nagata, "Low-Cost Distance-Spoofing Attack on FMCW Radar and Its Feasibility Study on Countermeasure," Springer Journal of Cryptographic Engineering, Online, pp. 1-10, Jan. 2021.DOI: 10.1007/s13389-020-00252-5

022

Ville Yli-Мäyry, Rei Ueno, Noriyuki Miura, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Naofumi Homma, "Diffusional Side-channel Leakage from Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE," IEEE Transactions on Information Forensics and Security, vol.16, pp. 1351-1364, 2021.DOI: 10.1109/TIFS.2020.3033441

023

Yoshihide Komatsu, Akinori Shinmyo, Mayuko Fujita, Tsuyoshi Hiraki, Kouichi Fukuda, Noriyuki Miura, Makoto Nagata, "0.6V Adaptive Voltage Swing Serial Link Transmitter Using near Threshold Body Bias Control and Jitter Estimation," IEICE Trans. Electron., vol. e103-c, no. 10, pp. 497-504, Oct 2020.DOI: 10.1587/transele.2019CTP0002

024

Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, "Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices," IEEE Journal of Solid-State Circuits (JSSC), vol. 55, no. 10, pp. 2747-2755, Oct. 2020.DOI: 10.1109/JSSC.2020.3005779

025

Tomoaki Mahiko, Taro Yoshikawa, Makoto Nagata, "Development of electro-copper plating with nanodiamonds for electronic interconnects in advanced packaging," Japanese Journal of Applied Physics, vol. 59, no. SLLD04, pp. 1-7, Jun. 2020.DOI: 10.35848/1347-4065/ab9588

026

Rei Ueno, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Naofumi Homma, "High Throughput/Gate AES Hardware Architectures Based on Datapath Compression," IEEE Transactions on Computers, vol. 69, no. 4, pp. 534-548, Apr. 2020.DOI: 10.1109/TC.2019.2957355

027

Hiroshi Suenaga, Akihiro Tsukioka, Kosuke Jike, Makoto Nagata, "Compact Simulation of Chip-to-Chip Active Noise Coupling on a System PCB Board," IEEE Letters on Electromagnetic Compatibility Practice and Applications (L-EMCPA), vol. 2, no. 1, pp.15-20, Mar. 2020.DOI: 10.1109/LEMCPA.2020.2983687

028

Akihiro Tsukioka, Karthik Srinivasan, Shan Wan, Lang Lin, Ying-Shiun Li, Norman Chang, Makoto Nagata, "A Fast Side-channel Leakage Simulation Technique Based on IC Chip Power Modeling," IEEE Letters on Electromagnetic Compatibility Practice and Applications (L-EMCPA), vol. 1, no. 4, pp. 83-87, Dec. 2019.DOI: 10.1109/LEMCPA.2020.2978624

029

Kohei Matsuda, Sho Tada, Makoto Nagata, Yuichi Komano, Yang Li, Takeshi Sugawara, Mitsugu Iwamoto, Kazuo Ohta, Kazuo Sakiyama and Noriyuki Miura, "An IC-level countermeasure against laser fault injection attack by information leakage sensing based on laser-induced opto-electric bulk current density," Japanese Journal of Applied Physics (JJAP), vol. 59, SGGL02, pp.1-12, Feb. 2020.DOI: 10.7567/1347-4065/ab65d3

030

Takuji Miki, Noriyuki Miura, Hiroki Sonoda, Kento Mizuta, Makoto Nagata, "A Random Interrupt Dithering SAR Technique for Secure ADC Against Reference-Charge Side-Channel Attack," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 1, pp.14-18, Jan. 2020.DOI: 10.1109/TCSII.2019.2901534

031

Koh Watanabe, Yoshifumi Sugimoto, Satoshi Tanaka, Noriyuki Miura, Makoto Nagata, Yasunori Miyazawa, Masahiro Yamaguchi, "Evaluation of Undesired Radio Waves below -170 dBm/Hz from Semiconductor Switching Devices for Impact on Wireless Communication," IEEE Letters on Electromagnetic Compatibility Practice and Applications, vol. 1, issue. 3, pp.72-76, Sep. 2019.DOI: 10.1109/LEMCPA.2020.2976990

032

Takuji Miki, Noriyuki Miura, Makoto Nagata, "A 0.72pJ/bit 400μm2 Physical Random Number Generator Utilizing SAR Technique for Secure Implementation on Sensor Nodes," IEICE Transactions on Electronics, Vol. E102-C, No. 7, pp. 530-537, Jul. 2019.DOI: 10.1587/transele.2018CTP0012

033

Takeshi Sugawara, Natsu Shoji, Kazuo Sakiyama, Kohei Matsuda, Noriyuki Miura, Makoto Nagata, "Side-channel leakage from sensor-based countermeasures against fault injection attack," Elsevier Microelectronics Journal, vol. 90, pp. 63-71, May. 2019.DOI: 10.1016/j.mejo.2019.05.017

034

Yuuki Araga, Makoto Nagata, Hiroaki Ikeda, Takuji Miki, Noriyuki Miura, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, "A Thick Cu Layer Buried in Si Interposer Backside for Global Power Routing," IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 9, No. 3, pp. 502-510, Mar. 2019.DOI: 10.1109/TCPMT.2018.2877211

035

Kohei Matsuda, Tatsuya Fujii, Natsu Shoji, Takeshi Sugawara, Kazuo Sakiyama, Yu-ichi Hayashi, Makoto Nagata, Noriyuki Miura, "A 286 F2/Cell Distributed Bulk-Current Sensor and Secure Flush Code Eraser Against Laser Fault Injection Attack on Cryptographic Processor," IEEE Journal of Solid-State Circuits, Vol. 53, No. 11, pp. 3174-3182, Sep. 2018.DOI: 10.1109/JSSC.2018.2869142

036

Noriyuki Miura, Masanori Takahashi, Kazuki Nagatomo, Makoto Nagata, "Chip-Package-Board Interactive PUF Utilizing Coupled Chaos Oscillators with Inductor," IEEE Journal of Solid-State Circuits, Vol. 53, No. 10, pp. 2889-2897, Jul. 2018.DOI: 10.1109/JSSC.2018.2852325

037

Daisuke Fujimoto, Shota Nin, Yu-ichi Hayashi, Noriyuki Miura, Makoto Nagata, Tsutomu Matsumoto, "A Demonstration of a HT-Detection Method Based on Impedance Measurements of the Wiring Around ICs," IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 65, No. 10, pp. 1320-1324, Jul. 2018.DOI: 10.1109/TCSII.2018.2858798

038

Yuuki Araga, Makoto Nagata, Joeri De Vos, Geert Van der Plas, Eric Beyne, "A Study on Substrate Noise Coupling among TSVs in 3D Chip Stack," IEICE Electronics Express, Vol. 15, No. 13, pp. 1-8, Jul. 2018.DOI: 10.1587/elex.15.20180460

039

山口正洋、田中聡、吉田栄吉、石山和志、永田真、近藤幸一、沖米田恭之、佐藤光晴、宮澤安範、畠山賢介, "（招待論文）不要電波の広帯域化に対応した電波環境計測技術と改善技術," 電子情報通信学会論文誌B分冊, Vol. J101–B, No. 3 pp. 204–211, Mar. 2018.DOI: 10.14923/transcomj.2017PEI0001

040

Yuuki Araga, Makoto Nagata, Noriyuki Miura, Hiroaki Ikeda, Katsuya Kikuchi, "Measurement and Analysis of Power Noise Characteristics for EMI Awareness of Power Delivery Networks in 3-D Through-Silicon Via Integration," IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 8, No. 2, pp. 277-285, Feb. 2018.DOI: 10.1109/TCPMT.2017.2767065

041

Takuji Miki, Toshiaki Ozeki, Jun-ichi Naka, "A 2-GS/s 8-bit Time-Interleaved SAR ADC for Millimeter-Wave Pulsed Radar Baseband SoC," IEEE Journal of Solid-State Circuits, Vol. 52, No. 10, pp. 2712-2720, Oct. 2017.DOI: 10.1109/JSSC.2017.2732732

042

Takuji Miki, Noriyuki Miura, Kento Mizuta, Shiro Dosho, Makoto Nagata, "A 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter Utilizing Two-Step Transition Inverter Delay Lines in 28 nm CMOS," IEICE Transactions on Electronics, Vol.E100-C, No. 6, pp. 560-567, Jun. 2017.DOI: 10.1587/transele.E100.C.560

043

Yuuki Araga, Makoto Nagata, Noriyuki Miura, Hiroaki Ikeda, Katsuya Kikuchi, "Superior decoupling capacitor for three-dimensional LSI with ultrawide communication bus," Japanese Journal of Applied Physics, Vol. 56, No. 4S, pp. 04CC05-1-04EE06-6, Apr. 2017.DOI: 10.7567/JJAP.56.04CC05

044

永田真, "（招待論文）VLSIシステムのノイズ問題克服に向けた研究の取組み―エレクトロニクスソサイエティ賞の受賞によせて―," 電子情報通信学会論文誌C分冊, Vol. J100-C, No. 2, pp. 82-90, Feb. 2017.DOI:

045

Makoto Nagata, Daisuke Fujimoto, Noriyuki Miura, Naofumi Homma, Yu-ichi Hayashi, Kazuo Sakiyama, "(Review paper) Protecting cryptographic integrated circuits with side-channel information," IEICE Electronics Express(ELEX), Vol. 14 No. 2 pp. 1-13, Feb. 2017.DOI: 10.1587/elex.14.20162005

046

Naofumi Homma, Yu-ichi Hayashi, Takafumi Aoki, Noriyuki Miura, Daisuke Fujimoto, Makoto Nagata, "Design Methodology and Validity Verification for a Reactive Countermeasure Against EM Attacks," IACR Journal of Cryptology, pp. 1-19, Online, Dec. 2015.DOI: 10.1007/s00145-015-9223-3

047

Makoto Nagata, Satoshi Takaya, Hiroaki Ikeda, "In-Place Signal and Power Noise Waveform Capturing Within 3-D Chip Stacking," IEEE Design and Test, Vol. 32, No. 6, pp. 87-98, Nov. 2015.DOI: 10.1109/MDAT.2015.2448537

048

Noriyuki Miura, Shiro Dosho, Hiroyuki Tezuka, Takuji Miki, Daisuke Fujimoto, Takuya Kiriyama, Makoto Nagata, "A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan," IEEE Journal of Solid-State Circuits, Vol. 50, No. 11, pp. 2741-2749, Nov. 2015.DOI: 10.1109/JSSC.2015.2480094

049

Takuya Sawada, Kumpei Yoshikawa, Hidehiro Takata, Koji Nii, Makoto Nagata, "An Extended Direct Power Injection Method for In-Place Susceptibility Characterization of VLSI Circuits Against Electromagnetic Interference," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 10, pp. 2347-2351, Oct. 2015.DOI: 10.1109/TVLSI.2014.2361208

050

Sho Endo, Yang Li, Naofumi Homma, Kazuo Sakiyama, Kazuo Ohta, Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Jean-Luc Danger, Takafumi Aoki, "A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 8, p. 1429-1438, Aug. 2015.DOI: 10.1109/TVLSI.2014.2339892

051

Takefumi Yoshikawa, Makoto Nagata, "Timing Margin Enhancement Technique for Current Mode Interface," IEICE Electronics Express, Vol. 11, No. 19, pp. 1-7, Sep. 2014.DOI: 10.1587/elex.11.20140766

052

Yuuki Araga, Makoto Nagata, Geert Van der Plas, Paul Marchal, Michael Libois, Antonio La Manna, Wenqi Zhang, Gerald Beyer, Eric Beyne, "Measurements and Analysis of Substrate Noise Coupling in TSV based 3D Integrated Circuits," IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 4, No. 6, pp. 1026-1037, Jun. 2014.DOI: 10.1109/TCPMT.2014.2316150

053

Satoshi Takaya, Hiroaki Ikeda, Makoto Nagata, "Diagnosis of Signaling and Power Noise Using In-Place Waveform Capturing for 3D Chip Stacking," IEICE Transactions on Electronics, Vol. E97-C, No. 6, pp. 557-565, Jun. 2014.DOI: 10.1587/transele.E97.C.557

054

Naoya Azuma, Shunsuke Shimazaki, Noriyuki Miura, Makoto Nagata, Tomomitsu Kitamura, Satoru Takahashi, Motoki Murakami, Kazuaki Hori, Atsushi Nakamura, Kenta Tsukamoto, Mizuki Iwanami, Eiji Hankui, Sho Muroga, Yasushi Endo, Satoshi Tanaka, Masahiro Yamaguchi, "Chip Level Simulation of Substrate Noise Coupling and Interference in RF ICs with CMOS Digital Noise Emulator," IEICE Transactions on Electronics, Vol. E97-C, No. 6, pp. 546-556, Jun. 2014.DOI: 10.1587/transele.E97.C.546

055

Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto, "A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation," IEICE Transactions on Electronics, Vol. E97-C, No. 4, pp. 332-341, Apr. 2014.DOI: 10.1587/transele.E97.C.332

056

Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yuichi Hayashi, Naofumi Homma, Takafumi Aoki, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Jean-Luc Danger, "Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage," IEICE Transactions on Electronics, Vol. E97-C, No. 4, pp. 272-279, Apr. 2014.DOI: 10.1587/transele.E97.C.272

057

Kumpei Yoshikawa, Kouji Ichikawa, Makoto Nagata, "AC Power Supply Noise Simulation of CMOS Microprocessor with LSI Chip-Package-Board Integrated Model," IEICE Transactions on Electronics, Vol. E97-C, No. 4, pp. 264-271, Apr. 2014.DOI: 10.1587/transele.E97.C.264

058

Shunsuke Shimazaki, Shota Taga, Tetsuya Makita, Naoya Azuma, Noriyuki Miura, Makoto Nagata, "Emulation of high-frequency substrate noise generation in CMOS digital circuits," Japanese Journal of Applied Physics, Vol. 53, No. 4S, pp. 04EE06-1-04EE06-6, Apr. 2014.DOI: 10.7567/JJAP.53.04EE06

059

Daisuke Fujimoto, Toshihiro Katashita, Akihiko Sasaki, Akashi Satoh, Makoto Nagata, "A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation," IEICE Transactions on Fundamentals, Vol. E96-A, No.12, pp. 2533-2541, Dec. 2013.DOI: 10.1587/transfun.E96.A.2533

060

Yuuki Araga, Nao Ueda, Yasumasa Takagi, Makoto Nagata, "Performance Evaluation of Probing Front-End Circuits for On-Chip Noise Monitoring," IEICE Transactions on Fundamentals, Vol. E96-A, No.12, pp. 2516-2523, Dec. 2013.DOI: 10.1587/transfun.E96.A.2516

061

Satoshi Takaya, Yoji Bando, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Soda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata, "Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation," IEICE Transactions on Electronics, Vol. E96-C, No. 6, pp. 884-893, Jun. 2013.DOI: 10.1587/transele.E96.C.884

062

Naoya Azuma, Makoto Nagata, "Equivalent Circuit Representation of Silicon Substrate Coupling of Passive and Active RF Components," IEICE Transactions on Electronics, Vol. E96-C, No. 6, pp. 875-883, Jun. 2013.DOI: 10.1587/transele.E96.C.875

063

Takuya Sawada, Hidehiro Takata, Koji Nii, Makoto Nagata, "False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation," Japanese Journal of Applied Physics, Vol. 52 , No. 4, pp. 04CE14-1-04CE14-5, Apr. 2013.DOI: 10.7567/JJAP.52.04CE14

064

Takeshi Okumoto, Kumpei Yoshikawa, Makoto Nagata, "Design of Effective Supply Voltage Monitor for Measuring Power Rails of Integrated Circuits," IEICE Transactions on Electronics, Vol. E96-C, No. 4, pp. 538-545, Apr. 2013.DOI: 10.1587/transele.E96.C.538

065

Kumpei Yoshikawa, Yuta Sasaki, Kouji Ichikawa, Yoshiyuki Saito, Makoto Nagata, "Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits," IEICE Transactions on Fundamentals, Vol. E95-A, No. 12, pp. 2284-2291, Dec. 2012.DOI: 10.1587/transfun.E95.A.2284

066

Takuya Sawada, Taku Toshikawa, Kumpei Yoshikawa, Hidehiro Takata, Koji Nii, Makoto Nagata, "Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation," IEICE Transactions on Electronics, Vol. E95-C, No. 4, pp. 586-593, Apr. 2012.DOI: 10.1587/transele.E95.C.586

067

Makoto Nagata, "Modeling and Analysis of Substrate Noise Coupling in Analog and RF ICs (Invited)," IEICE Transactions on Fundamentals, Vol. E95-A, No. 2, pp. 430-438, Feb. 2012.DOI: 10.1587/transfun.E95.A.430

068

Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Soda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata, "On-Chip In-Place Measurements of Vth and Signal/Substrate Response of Differential Pair Transistors," IEICE Transactions on Electronics, Vol. E95-C, No. 1, pp. 137-145, Jan. 2012.DOI: 10.1587/transele.E95.C.137

069

Sho Muroga, Yasushi Endo, Wataru Kodaate, Yoshiaki Sasaki, Kumpei Yoshikawa, Yuta Sasaki, Makoto Nagata, Masahiro Yamaguchi, "Evaluation of Thin Film Noise Suppressor Applied to Noise Emulator Chip Implemented in 65 nm CMOS Technology," IEEE Transactions on Magnetics, Vol. 47, No. 10, pp. 4485-4488, Oct. 2011.DOI: 10.1109/TMAG.2011.2157328

070

Masaaki Soda, Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro,Tohru Mogami, Makoto Nagata, "On-Chip Single Tone Psuedo-Noise Generator for Analog IP Noise Tolerance Measurement," IEICE Transactions on Electronics, Vol. E94-C, No. 6, pp. 1024-1031, Jun. 2011.DOI: 10.1587/transele.E94.C.1024

071

Takushi Hashida, Yuuki Araga, Makoto Nagata, "A Diagnosis Testbench of Analog IP Cores for Characterization of Substrate Coupling Strength," IEICE Transactions on Electronics, Vol. E94-C, No. 6, pp. 1016-1023, Jun. 2011.DOI: 10.1587/transele.E94.C.1016

072

Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Soda, Shigetaka Kumashiro,Tohru Mogami, Makoto Nagata, "A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits," IEICE Transactions on Electronics, Vol. E94-C, No. 4, pp. 495-503, Apr. 2011.DOI: 10.1587/transele.E94.C.495

073

Takushi Hashida, Makoto Nagata, "An On-Chip Waveform Capturer and Application to Diagnosis of Power Delivery in SoC Integration, "IEEE Journal of Solid-State Circuits, Vol. 46, No. 4, pp. 789-796, Apr. 2011.DOI: 10.1109/JSSC.2011.2108132