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学術講演(査読無し・予稿無し) 2013年

5 Makoto Nagata, "Power Noise Awareness in Design and Diagnosis of VLSI Systems," 2013 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), Keynote Speech III, 2013.12.13. (Nara)
4 Makoto Nagata, Sathoshi Takaya, Hiroaki Ikeda, "In-Place Signal and Power Noise Waveform Capturing within 3D Chip Stacking," Fourth IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST), #5-2, 2013.9.13, oral presentation. (Anaheim)
3 Makoto Nagata, Sathoshi Takaya, Hiroaki Ikeda, "In-Place Signal and Power Noise Waveform Capturing within 3D Chip Stacking," 2013 IEEE International Test Conference (ITC 2013), PO-27, 2013.9.11, poster presentation. (Anaheim)
Makoto Nagata, "Power-Noise Measurements and Simulation Techniques for Side-Channel Analysis," 2013 IEEE International Symposium on Electromagnetic Compatibility (EMC 2013), Tutorials MO-AM-4-3, 2013.8.5, tutorial talk 45 min. (Denver)
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Makoto Nagata, Sathoshi Takaya, Atsushi Sakai, Shiro Uchiyama, Harufumi Kobayashi, Hiroaki Ikeda, "Design Strategies using 2D Toolsets for 3D TSV Chip Stacks featuring 4096b Wide I/O at 100GB/s," Design Automation Conference 2013 (DAC 2013), Designer Track #7.29, 2013.6.5, poster presentation. (Austin)