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32 Takuji Miki, Noriyuki Miura, Kento Mizuta, Shiro Dosho, Makoto Nagata, "A 500 MHz-BW -52.5 dB-THD Voltage-to-Time Converter Utilizing Two-Step Transition Inverter Delay Lines in 28 nm CMOS," IEICE Transactions on Electronics, Vol.E100-C, No. 6, pp. 560-567, June 2017.
31 Yuuki Araga, Makoto Nagata, Noriyuki Miura, Hiroaki Ikeda, Katsuya Kikuchi, "Superior decoupling capacitor for three-dimensional LSI with ultrawide communication bus," Japanese Journal of Applied Physics, Vol. 56, No. 4S, pp. 04CC05-1-04EE06-6, Apr. 2017. DOI:10.7567/JJAP.56.04CC05
30 永田真, "(招待論文)VLSIシステムのノイズ問題克服に向けた研究の取組み―エレクトロニクスソサイエティ賞の受賞によせて―," 電子情報通信学会論文誌C分冊, Vol. J100-C, No. 2, pp. 82-90, Feb. 2017.
29 Makoto Nagata, Daisuke Fujimoto, Noriyuki Miura, Naofumi Homma, Yu-ichi Hayashi, Kazuo Sakiyama, "(Review paper) Protecting cryptographic integrated circuits with side-channel information," IEICE Electronics Express(ELEX), Vol. 14 No. 2 pp. 1-13, Feb. 2017. DOI: 10.1587/elex.14.20162005
28 Naofumi Homma, Yu-ichi Hayashi, Takafumi Aoki, Noriyuki Miura, Daisuke Fujimoto, Makoto Nagata, "Design Methodology and Validity Verification for a Reactive Countermeasure Against EM Attacks," IACR Journal of Cryptology, pp. 1-19, Online, Dec. 2015.
27 Makoto Nagata, Satoshi Takaya, Hiroaki Ikeda, "In-Place Signal and Power Noise Waveform Capturing Within 3-D Chip Stacking," IEEE Design and Test, Vol. 32, No. 6, pp. 87-98, Nov. 2015.
26 Noriyuki Miura, Shiro Dosho, Hiroyuki Tezuka, Takuji Miki, Daisuke Fujimoto, Takuya Kiriyama, Makoto Nagata, "A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan," IEEE Journal of Solid-State Circuits, Vol. 50, No. 11, pp. 2741-2749, Nov. 2015.
25 Takuya Sawada, Kumpei Yoshikawa, Hidehiro Takata, Koji Nii, Makoto Nagata, "An Extended Direct Power Injection Method for In-Place Susceptibility Characterization of VLSI Circuits Against Electromagnetic Interference," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 10, pp. 2347-2351, Oct. 2015.
24 Sho Endo, Yang Li, Naofumi Homma, Kazuo Sakiyama, Kazuo Ohta, Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Jean-Luc Danger, Takafumi Aoki, "A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 8, p. 1429-1438, Aug. 2015.
23 Takefumi Yoshikawa, Makoto Nagata, "Timing Margin Enhancement Technique for Current Mode Interface," IEICE Electronics Express, Vol. 11, No. 19, pp. 1-7, Sep. 2014.
22 Yuuki Araga, Makoto Nagata, Geert Van der Plas, Paul Marchal, Michael Libois, Antonio La Manna, Wenqi Zhang, Gerald Beyer, Eric Beyne, "Measurements and Analysis of Substrate Noise Coupling in TSV based 3D Integrated Circuits," IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 4, No. 6, pp. 1026-1037, June 2014.
21 Satoshi Takaya, Hiroaki Ikeda, Makoto Nagata, "Diagnosis of Signaling and Power Noise Using In-Place Waveform Capturing for 3D Chip Stacking," IEICE Transactions on Electronics, Vol. E97-C, No. 6, pp. 557-565, June 2014.
20 Naoya Azuma, Shunsuke Shimazaki, Noriyuki Miura, Makoto Nagata, Tomomitsu Kitamura, Satoru Takahashi, Motoki Murakami, Kazuaki Hori, Atsushi Nakamura, Kenta Tsukamoto, Mizuki Iwanami, Eiji Hankui, Sho Muroga, Yasushi Endo, Satoshi Tanaka, Masahiro Yamaguchi, "Chip Level Simulation of Substrate Noise Coupling and Interference in RF ICs with CMOS Digital Noise Emulator," IEICE Transactions on Electronics, Vol. E97-C, No. 6, pp. 546-556, June 2014.
19 Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto, "A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation," IEICE Transactions on Electronics, Vol. E97-C, No. 4, pp. 332-341, Apr. 2014.
18 Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yuichi Hayashi, Naofumi Homma, Takafumi Aoki, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Jean-Luc Danger, "Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage," IEICE Transactions on Electronics, Vol. E97-C, No. 4, pp. 272-279, Apr. 2014.
17 Kumpei Yoshikawa, Kouji Ichikawa, Makoto Nagata, "AC Power Supply Noise Simulation of CMOS Microprocessor with LSI Chip-Package-Board Integrated Model," IEICE Transactions on Electronics, Vol. E97-C, No. 4, pp. 264-271, Apr. 2014.
16 Shunsuke Shimazaki, Shota Taga, Tetsuya Makita, Naoya Azuma, Noriyuki Miura, Makoto Nagata, "Emulation of high-frequency substrate noise generation in CMOS digital circuits," Japanese Journal of Applied Physics, Vol. 53, No. 4S, pp. 04EE06-1-04EE06-6, Apr. 2014.

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Daisuke Fujimoto, Toshihiro Katashita, Akihiko Sasaki, Akashi Satoh, Makoto Nagata, "A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation," IEICE Transactions on Fundamentals, Vol. E96-A, No.12, pp. 2533-2541, Dec. 2013.
14 Yuuki Araga, Nao Ueda, Yasumasa Takagi, Makoto Nagata, "Performance Evaluation of Probing Front-End Circuits for On-Chip Noise Monitoring," IEICE Transactions on Fundamentals, Vol. E96-A, No.12, pp. 2516-2523, Dec. 2013.
13 Satoshi Takaya, Yoji Bando, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Soda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata, "Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation," IEICE Transactions on Electronics, Vol. E96-C, No. 6, pp. 884-893, June 2013.
12 Naoya Azuma, Makoto Nagata, "Equivalent Circuit Representation of Silicon Substrate Coupling of Passive and Active RF Components," IEICE Transactions on Electronics, Vol. E96-C, No. 6, pp. 875-883, June 2013.
11 Takuya Sawada, Hidehiro Takata, Koji Nii, Makoto Nagata, "False Operation of Static Random Access Memory Cells under Alternating Current Power Supply Voltage Variation," Japanese Journal of Applied Physics, Vol. 52 , No. 4, pp. 04CE14-1-04CE14-5, Apr. 2013.
10 Takeshi Okumoto, Kumpei Yoshikawa, Makoto Nagata, "Design of Effective Supply Voltage Monitor for Measuring Power Rails of Integrated Circuits," IEICE Transactions on Electronics, Vol. E96-C, No. 4, pp. 538-545, Apr. 2013.
9 Kumpei Yoshikawa, Yuta Sasaki, Kouji Ichikawa, Yoshiyuki Saito, Makoto Nagata, "Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits," IEICE Transactions on Fundamentals, Vol. E95-A, No. 12, pp. 2284-2291, Dec. 2012.
8 Takuya Sawada, Taku Toshikawa, Kumpei Yoshikawa, Hidehiro Takata, Koji Nii, Makoto Nagata, "Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation," IEICE Transactions on Electronics, Vol. E95-C, No. 4, pp. 586-593, Apr. 2012.
7 Makoto Nagata, "Modeling and Analysis of Substrate Noise Coupling in Analog and RF ICs (Invited)," IEICE Transactions on Fundamentals, Vol. E95-A, No. 2, pp. 430-438, Feb. 2012.
6 Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Soda, Shigetaka Kumashiro, Tohru Mogami, Makoto Nagata, "On-Chip In-Place Measurements of Vth and Signal/Substrate Response of Differential Pair Transistors," IEICE Transactions on Electronics, Vol. E95-C, No. 1, pp. 137-145, Jan. 2012.
5 Sho Muroga, Yasushi Endo, Wataru Kodaate, Yoshiaki Sasaki, Kumpei Yoshikawa, Yuta Sasaki, Makoto Nagata, Masahiro Yamaguchi, "Evaluation of Thin Film Noise Suppressor Applied to Noise Emulator Chip Implemented in 65 nm CMOS Technology," IEEE Transactions on Magnetics, Vol. 47, No. 10, pp. 4485-4488, Oct. 2011.
DOI: 10.1109/TMAG.2011.2157328
4 Masaaki Soda, Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Shigetaka Kumashiro,Tohru Mogami, Makoto Nagata, "On-Chip Single Tone Psuedo-Noise Generator for Analog IP Noise Tolerance Measurement," IEICE Transactions on Electronics, Vol. E94-C, No. 6, pp. 1024-1031, June 2011.
3 Takushi Hashida, Yuuki Araga, Makoto Nagata, "A Diagnosis Testbench of Analog IP Cores for Characterization of Substrate Coupling Strength," IEICE Transactions on Electronics, Vol. E94-C, No. 6, pp. 1016-1023, June 2011.
2 Yoji Bando, Satoshi Takaya, Toru Ohkawa, Toshiharu Takaramoto, Toshio Yamada, Masaaki Soda, Shigetaka Kumashiro,Tohru Mogami, Makoto Nagata, "A Continuous-Time Waveform Monitoring Technique for On-Chip Power Noise Measurements in VLSI Circuits," IEICE Transactions on Electronics, Vol. E94-C, No. 4, pp. 495-503, Apr. 2011.
1 Takushi Hashida, Makoto Nagata, "An On-Chip Waveform Capturer and Application to Diagnosis of Power Delivery in SoC Integration, "IEEE Journal of Solid-State Circuits, Vol. 46, No. 4, pp. 789-796, Apr. 2011.