||Takefumi Yoshikawa, Makoto Nagata, "Timing Margin Enhancement Technique for Current Mode Interface," IEICE Electronics Express, Vol. 11, No. 19, pp. 1-7, Sep. 2014.
||Yuuki Araga, Makoto Nagata, Geert Van der Plas, Paul Marchal, Michael Libois, Antonio La Manna, Wenqi Zhang, Gerald Beyer, Eric Beyne, "Measurements and Analysis of Substrate Noise Coupling in TSV based 3D Integrated Circuits," IEEE Transactions on Components, Packaging and Manufacturing Technology, Vol. 4, No. 6, pp. 1026-1037, June 2014.
||Satoshi Takaya, Hiroaki Ikeda, Makoto Nagata, "Diagnosis of Signaling and Power Noise Using In-Place Waveform Capturing for 3D Chip Stacking," IEICE Transactions on Electronics, Vol. E97-C, No. 6, pp. 557-565, June 2014.
||Naoya Azuma, Shunsuke Shimazaki, Noriyuki Miura, Makoto Nagata, Tomomitsu Kitamura, Satoru Takahashi, Motoki Murakami, Kazuaki Hori, Atsushi Nakamura, Kenta Tsukamoto, Mizuki Iwanami, Eiji Hankui, Sho Muroga, Yasushi Endo, Satoshi Tanaka, Masahiro Yamaguchi, "Chip Level Simulation of Substrate Noise Coupling and Interference in RF ICs with CMOS Digital Noise Emulator," IEICE Transactions on Electronics, Vol. E97-C, No. 6, pp. 546-556, June 2014.
||Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto, "A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation," IEICE Transactions on Electronics, Vol. E97-C, No. 4, pp. 332-341, Apr. 2014.
||Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yuichi Hayashi, Naofumi Homma, Takafumi Aoki, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Jean-Luc Danger, "Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage," IEICE Transactions on Electronics, Vol. E97-C, No. 4, pp. 272-279, Apr. 2014.
||Kumpei Yoshikawa, Kouji Ichikawa, Makoto Nagata, "AC Power Supply Noise Simulation of CMOS Microprocessor with LSI Chip-Package-Board Integrated Model," IEICE Transactions on Electronics, Vol. E97-C, No. 4, pp. 264-271, Apr. 2014.
||Shunsuke Shimazaki, Shota Taga, Tetsuya Makita, Naoya Azuma, Noriyuki Miura, Makoto Nagata, "Emulation of high-frequency substrate noise generation in CMOS digital circuits," Japanese Journal of Applied Physics, Vol. 53, No. 4S, pp. 04EE06-1-04EE06-6, Apr. 2014.